Verilog Signed Multiplication“失去”有符号位

我正在编写一个使用乘法器模块的代码，当其中一个输入是负数时，它会返回奇怪的答案 . 我猜这与Verilog如何处理已签名的数字有关，而且该模块没有正确地将结果存储在'reg signed out'decleration中 . 我所有的输入/输出/连线/注册声明都是签名的，所以我不确定我错过了什么以及我需要做些什么来告诉Verilog来处理这个问题 . 对不起初学者的问题！

例如，

当X [0]为1610且Theta1 [1]为-123时，我从乘法器模块得到的结果是：6914897148530

以下是我的代码的相关部分：

module mult(in1, in2, out, mult_start); // multiplication module

input signed    [32-1:0]    in1, in2;
input               mult_start;

output      signed [64-1:0] out;
reg         signed [64-1:0] out;

always @(in1 or in2 or mult_start)
begin
    if (mult_start)
    begin
        out <= (in1 * in2) & {64{1'b1}};
    end
    else
        out <= out;
end
endmodule



module child_one (clk, rst_b, sig_start, Input_X, Input_Theta1)

// Internal Variables Memory
reg signed [`REG_LENGTH-1:0] Theta1 [0:217-1];
reg signed [`REG_LENGTH-1:0] X [0:216-1];
wire signed [`OUT_LENGTH-1:0] prod_1 [0:217-1];
reg signed [`OUT_LENGTH-1:0] prod_sum;
wire signed [`OUT_LENGTH-1:0] sig_result;

mult mult_001 (X[0], Theta1[1], prod_1[1], mult_start); 
mult mult_002 (X[1], Theta1[2], prod_1[2], mult_start); 
mult mult_003 (X[2], Theta1[3], prod_1[3], mult_start); 
mult mult_004 (X[3], Theta1[4], prod_1[4], mult_start); 

always @(posedge clk or negedge rst_b)
begin
    if (sig_start == 1) 
    begin
        if (state == 4'b0000)
        begin
            state <= 4'b0001; // initialize state variable to zero
            k <= 0;
            result_done <= 0;
            index <= 0;
        end
        else if (state == 4'b0001) // Start Multiplication Operation
        begin
            k               <= result_done ?      0     : k + 1;
            result_done     <= result_done ?      1     : (k == 10);
            state       <= result_done ?      4'b0010   : 4'b0001;
            mult_start  <= result_done ?      1'b1  : 1'b0; 
        //mult_start <= 1'b1;
        //state <= 4'b0010;
        end
        else if (state == 4'b0010) // Stop Multiplication Operation
        begin
            k <= 0;
            result_done <= 0;
            mult_start <= 0;
            state <= 4'b0011;
        end
    end
end

endmodule

谢谢，

费萨尔 .