> Wires are used for connecting different elements. They can be treated
> as physical wires. They can be read or assigned. No values get stored
> in them. They need to be driven by either continuous assign statement
> or from a port of a module.
Reg:-
> Contrary to their name, regs don't necessarily correspond to
> physical registers. They represent data storage elements in
> Verilog/SystemVerilog. They retain their value till next value is
> assigned to them (not through assign statement). They can be
> synthesized to FF, latch or combinatorial circuit. (They might not be
> synthesizable !!!)
3 回答
Wire:-
Reg:-
Logic:-
程序块指的是
always
,always_ff
,always_comb
,always_latch
,initial
等块 . 程序赋值语句是指将值分配给reg,整数等, but not wire(网络) .wire
元素必须是 continuously driven 的东西,并且不能存储值 . 此后,使用 continuous assignment 语句为它们分配值 .reg
可用于在程序块中创建 registers . 因此,它可以 store 一些 Value .reg
elements can 用作输出 within 实际模块 declaration . 但是,reg
elements cannot 连接到模块 instantiation 的输出端口 .因此,reg可以将一条线作为
assign
声明 . 在另一方面,一根电线可以作为程序块的 RHS 驱动一个寄存器 .有关
reg
或wire
声明的明确说明,请参考下图:因此,每当推断存储/保存某些值的顺序逻辑时,将该变量/端口声明为
reg
. 这里,Q
是一个reg
inside 一个模块,但是当这个模块在其他模块中时_1145290_,那么这个端口必须连接到wire
.请记住,
wire
只能推断出组合逻辑,而reg
可以推断出组合逻辑或顺序逻辑 .戴夫的博客是详细信息的良好来源 . 有关详细信息,请参阅synthesizing difference和Verilog wire-reg链接 .
reg和wire之间的简单区别是,reg用于verilog中的组合或时序电路,而有线用于组合电路