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意外的高阻抗状态

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我在模块的输出端口遇到了意外的高阻抗状态问题 . 实例化其他模块的模块代码如下:

`timescale 1ns/1ps

module column(
    input wire clk,
    input wire reset,
    input wire trigger,
    input wire [7:0] latency
    );

localparam AMOUNT_OF_REGIONS = 3;

wire [24:0] o_data [0:AMOUNT_OF_REGIONS-1];
wire [1:0] up_in [0:AMOUNT_OF_REGIONS-1];
//same declarations for do_in, up_out, do_out

assign up_in[0] = 0;
assign do_in[AMOUNT_OF_REGIONS-1] = 0;

generate
    genvar i;
    for (i = 0; i < AMOUNT_OF_REGIONS; i = i + 1) begin : multiple_regions_instantiation
        if ((i == 0) || (i == AMOUNT_OF_REGIONS-1)) begin
            region tmp(
                clk,
                reset,
                trigger,
                latency,
                up_in[i],
                do_in[i],
                up_out[i],
                do_out[i],
                o_data[i]
            );
        end
        else begin
            region tmp(
                clk,
                reset,
                trigger,
                latency,
                do_out[i-1],
                up_out[i+1],
                do_in[i-1],
                up_in[i+1],
                o_data[i]
            );
        end
    end
endgenerate

endmodule

可实例化模块的端口声明如下:

module region(
    input wire clk,
    input wire reset,
    input wire trigger,
    input wire [7:0] latency,
    input wire [1:0] up,
    input wire [1:0] do,
    output reg [1:0] to_up,
    output reg [1:0] to_do,
    output reg [24:0] odata
    );

输出的分配在初始块中进行,如下所示:

initial begin
    latency_cnt = 255;
    start_cnt = 0;
    preset = 0;
    read_out = 0;
    begin: hit_generation
        cnt = 0;
        forever begin
            cnt = cnt + 1;
            fork
                #20 hit0 = ($random > 0) ? 1 : 0;
                #20 hit1 = ($random > 0) ? 1 : 0;
                #20 hit2 = ($random > 0) ? 1 : 0;
                #20 hit3 = ($random > 0) ? 1 : 0;
                to_up = {hit1, hit0};
                to_do = {hit3, hit2};
            join
            if (cnt == 10000) disable hit_generation;
        end
    end
end

所以,现在的问题是,如果AMOUNT_OF_REGIONS == 3或2,那么一切正常,但如果我试图增加其值,那么对于介于1和AMOUNT_OF_REGIONS-2(包括)之间的所有区域,他们的输入和输出混乱(2'bzz) . 但是0区域很好地向区域1发送信息,并且AMOUNT_OF_REGIONS-1区域将信息正确地发送给它的邻居 . 测试平台只是实例化一个列并生成一个触发器和clk信号 . 我已经读过,如果只有导线连接没有连接寄存器而导致高阻抗状态,但据我所见,我将导线连接到输出寄存器......亲爱的,可能是什么它的问题?我正在使用Icarus Verilog,如果重要的话 .

1 Answer

  • 0

    无意中,我找到了问题的根源 . 我会留下一个答案,也许有一天会对那些陷入这种情况的人有所帮助 .

    我做错了端口分配,所以,我想,他们是循环或类似的东西 . 问题在于:

    region tmp(
        clk,
        reset,
        trigger,
        latency,
        do_out[i-1],
        up_out[i+1],
        do_in[i-1],
        up_in[i+1],
        o_data[i]
    );
    

    我将模块的输入端口分配给另一个的输出,这是错误的......

    因此,在这种情况下分配端口的正确方法是这样的(实例化循环的完整代码):

    generate
        genvar i;
        for (i = 0; i < AMOUNT_OF_REGIONS; i = i + 1) begin : multiple_regions_instantiation
            if (i == 0) begin
                region tmp(
                    clk,
                    reset,
                    trigger,
                    latency,
                    up_in[i],
                    do_in[i],
                    up_out[i],
                    up_in[i+1], //CHANGED
                    o_data[i]
                );
            end
            else if (i == AMOUNT_OF_REGIONS-1) begin
                region tmp(
                    clk,
                    reset,
                    trigger,
                    latency,
                    up_in[i],
                    do_in[i],
                    do_in[i-1], //CHANGED
                    do_out[i],
                    o_data[i]
                );
            end
            else begin
                region tmp(
                    clk,
                    reset,
                    trigger,
                    latency,
                    up_in[i], //CHANGED
                    do_in[i], //CHANGED
                    do_in[i-1],
                    up_in[i+1],
                    o_data[i]
                );
            end
        end
    endgenerate
    

    希望它会帮助别人!

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