如何在System Verilog中实例化

我试图在System Verilog中实例化一个模块 . 它在Modelsim中编译没有问题 . 当我试图模拟测试平台时，它说 .

# Loading work.testbench_serial_reader
# ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.4a/examples/Serial_Read.sv(30): Instantiation of 'UARC' failed. The design unit was not found.
#    Time: 0 ns  Iteration: 0  Instance: /testbench_serial_reader File: C:/Modeltech_pe_edu_10.4a/examples/Serial_Read.sv
#         Searched libraries:
#             C:/Modeltech_pe_edu_10.4a/examples/work
# Error loading design

这是我的代码：

`default_nettype none







module testbench_serial_reader();

    reg clk, serial_in;
    reg [8:0] i; 
    wire [6:0] serial_out;
    wire new_data;
    reg  data[22];


    initial begin
        clk <= 0;
        serial_in <= 0;
        data = {0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1};
        i = 0;
        serial_in = data[i];
    end

    always #1 clk = ~clk;
    always #16 i = i + 1;
    always #16 serial_in = data[i];

    UARC serial_reader( serial_in, clk, serial_out, new_data);



endmodule











module serial_reader
(
input wire serial_in_async
,input wire clk
,output reg [6:0] parallel_out
,output reg new_data
);


    //reg [8:0] counter;
    reg [7:0] state;
    reg serial_in, serial_in_async2;
    //reg [1:0] state;
    reg [6:0] result;
    //reg add;

    initial
    begin
        state = 8'd0;
        serial_in = 1'b1;
        serial_in_async2 = 1'b1;
        result = 7'd0;
        new_data = 1'b0;
    end

    always @(posedge clk)
    begin

        serial_in = serial_in_async2;
        serial_in_async2 = serial_in_async;

        case (state)
            8'd0: if(~serial_in) begin 
                    state <= state + 1'd1;
                end
            8'd7: begin
                    if(~serial_in) begin
                        state <= state + 8'd1;
                        result <= 7'd0; 
                    end else state <= 8'd0;
                end
            8'd23: begin 
                    state <= state + 8'd1;
                    result <= result + serial_in;
                end
            8'd39: begin 
                    state <= state + 8'd1;
                    if(serial_in) begin
                        result <= result + 7'b0000010;
                    end
                end
            9'd55: begin 
                    state <= state + 8'd1;
                    if(serial_in) begin
                        result <= result + 7'b0000100;
                    end
                end
            9'd71: begin 
                    state <= state + 8'd1;
                    if(serial_in) begin
                        result <= result + 7'b0001000;
                    end
                end
            9'd87: begin 
                    state <= state + 8'd1;
                    if(serial_in) begin
                        result <= result + 7'b0010000;
                    end
                end
            9'd103: begin 
                    state <= state + 8'd1;
                    if(serial_in) begin
                        result <= result + 7'b0100000;
                    end
                end
            9'd119: begin 
                    state <= state + 8'd1;
                    if(serial_in) begin
                        result <= result + 7'b1000000;
                    end
                    new_data = 0;
                end
            9'd151: begin 
                    if(serial_in) begin
                        state <= state + 1; 
                    end else state <= 8'd136;
                    parallel_out = result;
                    new_data = 1;
                end
            9'd167: begin 
                    if(serial_in) begin
                        state <= 0; 
                    end else state <= 8'd152;
                end
            default: state <= state + 8'd1;
        endcase
    end
endmodule

知道问题可能是什么？当我编译和模拟verilog代码时，我没有得到实例化问题 . 只有系统Verilog . 我已经查看了许多代码示例，并且没有看到我如何进行实例化的问题 .