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Verilog:读取1位输入并将其写入288位reg

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在verilog中,我有 module name(input data,..., output...);
数据只是一位输入,我需要将它显示到 reg [288:0] data_tmp; 以比较这些位 . 如何将数据(输入)传输到reg?

我尝试使用for循环像C中的数组一样处理它,如下所示:

for(i=0; i<288; i=i+1) begin
    data_tmp[i]=data;
end

但它似乎不会从数据中获取任何值,也不会覆盖它们 .

实际代码:

module inspector (
input rst_n, data, clk,
output total_cnt, skype_cnt, ftp_cnt, https_cnt, telnet_cnt, ssh_cnt, snmp_cnt, smtp_cnt,
      nntp_cnt, telnet_session, skype_session, ssh_session
);

output [31:0] total_cnt;
output [7:0] skype_cnt;
output [7:0] ftp_cnt;
output [7:0] https_cnt;
output [7:0] telnet_cnt;
output [7:0] ssh_cnt;
output [7:0] snmp_cnt;
output [7:0] smtp_cnt;
output [7:0] nntp_cnt;
output [7:0] telnet_session;
output [7:0] skype_session;
output [7:0] ssh_session;

localparam INIT  = 0;
localparam DATA = 1;
localparam PORT = 2;
localparam TOTAL = 3;


reg [287:0] data_tmp;

reg [3:0] Start_sequence = 32'hA5A5A5A5;

reg [1:0] state;

integer i;

always @(posedge clk)

    if (rst_n) begin
        total_cnt_tmp = 8'h00;
        ....
        ssh_session_tmp = 8'h00;
    end else begin
        case (state)
            INIT    : begin
                for(i=0; i<288; i=i+1) begin
                    data_tmp[i]=data;
                end

                if (data_tmp[31:0] == Start_sequence) begin
                    state <= DATA;
                end else begin
                    state <= INIT;          
                end
            end
   .....

1 Answer

  • 0

    for循环正在复制数据;即如果 data 为1则得到288个,如果 data 为0则得到288个零 . 你想要的是什么是变速器 . data_tmp 根据比特流的顺序将比特向左或向右移位 .

    data_tmp<={data_tmp[286:0],data}; // shift and fill left
    

    要么

    data_tmp<={data,data_tmp[287:1]}; // shift and fill right
    

    另外,请记住分配具有非阻塞的触发器( <= ) . 阻止( = )分配组合逻辑 .

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