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VHDL：将std_logic_vector转换为整数时出错

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我正在vhdl（xilinx）中为数字转速计编写代码 . 将 std_logic_vector m1转换为整数时，编译器会显示以下错误 .

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity tacho is
    Port ( A : in  STD_LOGIC;
           B : out  STD_LOGIC_vector (15 downto 0));
end tacho;

architecture Behavioral of tacho is
component counter
            port(
            clk: in std_logic;
            m: out std_logic_vector (4 downto 0));
end component;
signal m1 : std_logic_vector (4 downto 0); 
variable y: integer := 0;
variable z: integer := 0;           
begin
x: counter port map(A,m1);
y:= to_integer(unsigned(m1)); --error1:Syntax error near ":=". error2:Expecting type  void for <to_integer>.
z:= y * 60; --Syntax error near ":=".
B <= std_logic_vector(to_unsigned(z, 16));
end Behavioral;

我在很多网站上发现我写的语法是正确的 . 请帮忙！

vhdl

2 回答

  • 1

    变量 y 和 z 无法在体系结构级别声明 . 改为使用信号，信号分配 <= ，如：

    ...
  signal y : integer;
  signal z: integer := 0;           
begin
  x: counter port map(A, m1);
  y <= to_integer(unsigned(m1));
  z <= y * 60;
  B <= std_logic_vector(to_unsigned(z, 16));
...

    或者简单地将它组合起来并避免中间体 y 和 z ，如：

    ...
  x: counter port map(A, m1);
  B <= std_logic_vector(resize(60 * unsigned(m1), B'length));
  ...
    回复于
  • 1

    非共享变量只能在流程语句或子程序中声明 . 您可以将缩放代码放在一个过程中：

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tacho is
    port ( A:   in  std_logic;
           B:   out std_logic_vector (15 downto 0)
    );
end entity tacho;

architecture behavioral of tacho is
    component counter is
        port (
            clk: in  std_logic;
            m:   out std_logic_vector (4 downto 0)
        );
    end component;
    signal m1 : std_logic_vector (4 downto 0);
begin

x: counter port map (A, m1);

scaling:
    process (m1)
        variable y: integer := 0;
        variable z: integer := 0;
    begin
        y := to_integer(unsigned(m1));
        z := y * 60;
        B <= std_logic_vector(to_unsigned(z, 16));
    end process;
end architecture behavioral;

    或者您可以将计算移动到子程序：

    architecture scaled of tacho is
    component counter is
        port (
            clk: in  std_logic;
            m:   out std_logic_vector (4 downto 0)
        );
    end component;
    signal m1 : std_logic_vector (4 downto 0);
    function scale(m1: std_logic_vector (4 downto 0); SIZE: natural := 16)
            return std_logic_vector is
        variable y: integer;
        variable z: integer;
    begin
        y := to_integer(unsigned(m1));
        z := y * 60;
        return std_logic_vector(to_unsigned(z, SIZE));
    end function;
begin

x: counter port map (A, m1);
scaled_output:
    B <= scale(m1);
end architecture;

    这两个分析 .

    回复于

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