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VHDL中的Wait语句错误

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我从this site读取了Quartus II 9.1中VHDL的位加法器 . 首先,根据指南我添加并编译1位加法器 - 它正常工作 .

-- Simulation Tutorial
-- 1-bit Adder

-- This is just to make a reference to some common things needed.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- We declare the 1-bit adder with the inputs and outputs
-- shown inside the port().
-- This will add two bits together(x,y), with a carry in(cin) and 
-- output the sum(sum) and a carry out(cout).
entity BIT_ADDER is
        port( a, b, cin         : in  STD_LOGIC;
              sum, cout         : out STD_LOGIC );
end BIT_ADDER;

-- This describes the functionality of the 1-BIT adder.
architecture BHV of BIT_ADDER is
begin

        -- Calculate the sum of the 1-BIT adder.
        sum <=  (not a and not b and cin) or
                        (not a and b and not cin) or
                        (a and not b and not cin) or
                        (a and b and cin);

        -- Calculates the carry out of the 1-BIT adder.
        cout <= (not a and b and cin) or
                        (a and not b and cin) or
                        (a and b and not cin) or
                        (a and b and cin);
end BHV;

当我编译它时,它工作正常 . 之后我添加其他VHDL来测试它 . 这是1位加法器的测试平台:

-- ENGR 10 VHDL Lab
-- 1-bit Adder Testbench

-- A testbench is used to rigorously tests a design that you have made.
-- The output of the testbench should allow the designer to see if
-- the design worked.  The testbench should also report where the testbench
-- failed.

-- This is just to make a reference to some common things needed.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Decare a testbench.  Notice that the testbench does not have any
-- input or output ports.
entity TEST_ADD is
end TEST_ADD;

-- Describes the functionality of the tesbench.
architecture TEST of TEST_ADD is 

    -- The object that we wish to test is declared as a component of 
    -- the test bench. Its functionality has already been described elsewhere.
    -- This simply describes what the object's inputs and outputs are, it
    -- does not actually create the object.
    component BIT_ADDER 
        port( a, b, cin         : in  STD_LOGIC;
            sum, cout         : out STD_LOGIC );
    end component;

    -- Specifies which description of the adder you will use.
    for U1: BIT_ADDER use entity WORK.BIT_ADDER(BHV);

    -- Create a set of signals which will be associated with both the inputs
    -- and outputs of the component that we wish to test.
    signal A_s, B_s : STD_LOGIC;
    signal CIN_s    : STD_LOGIC;
    signal SUM_s    : STD_LOGIC;
    signal COUT_s   : STD_LOGIC;

    -- This is where the testbench for the BIT_ADDER actually begins.   
    begin

    -- Create a 1-bit adder in the testbench.   
    -- The signals specified above are mapped to their appropriate
    -- roles in the 1-bit adder which we have created.
    U1: BIT_ADDER port map (A_s, B_s, CIN_s, SUM_s, COUT_s);

    -- The process is where the actual testing is done.
    process
    begin

        -- We are now going to set the inputs of the adder and test
        -- the outputs to verify the functionality of our 1-bit adder.

        -- Case 0 : 0+0 with carry in of 0.

        -- Set the signals for the inputs.
        A_s <= '0';
        B_s <= '0';
        CIN_s <= '0';

        -- Wait a short amount of time and then check to see if the 
        -- outputs are what they should be. If not, then report an error
        -- so that we will know there is a problem.
        wait for 10 ns;
        assert ( SUM_s = '0'  ) report "Failed Case 0 - SUM" severity error;
        assert ( COUT_s = '0' ) report "Failed Case 0 - COUT" severity error;
        wait for 40 ns;

        -- Carry out the same process outlined above for the other 7 cases.

        -- Case 1 : 0+0 with carry in of 1.
        A_s <= '0';
        B_s <= '0';
        CIN_s <= '1';
        wait for 10 ns;
        assert ( SUM_s = '1'  ) report "Failed Case 1 - SUM" severity error;
        assert ( COUT_s = '0' ) report "Failed Case 1 - COUT" severity error;
        wait for 40 ns;

        -- Case 2 : 0+1 with carry in of 0.
        A_s <= '0';
        B_s <= '1';
        CIN_s <= '0';
        wait for 10 ns;
        assert ( SUM_s = '1'  ) report "Failed Case 2 - SUM" severity error;
        assert ( COUT_s = '0' ) report "Failed Case 2 - COUT" severity error;
        wait for 40 ns;

        -- Case 3 : 0+1 with carry in of 1.
        A_s <= '0';
        B_s <= '1';
        CIN_s <= '1';
        wait for 10 ns;
        assert ( SUM_s = '0'  ) report "Failed Case 3 - SUM" severity error;
        assert ( COUT_s = '1' ) report "Failed Case 3 - COUT" severity error;
        wait for 40 ns;

        -- Case 4 : 1+0 with carry in of 0.
        A_s <= '1';
        B_s <= '0';
        CIN_s <= '0';
        wait for 10 ns;
        assert ( SUM_s = '1'  ) report "Failed Case 4 - SUM" severity error;
        assert ( COUT_s = '0' ) report "Failed Case 4 - COUT" severity error;
        wait for 40 ns;

        -- Case 5 : 1+0 with carry in of 1.
        A_s <= '1';
        B_s <= '0';
        CIN_s <= '1';
        wait for 10 ns;
        assert ( SUM_s = '0'  ) report "Failed Case 5 - SUM" severity error;
        assert ( COUT_s = '1' ) report "Failed Case 5 - COUT" severity error;
        wait for 40 ns;

        -- Case 6 : 1+1 with carry in of 0.
        A_s <= '1';
        B_s <= '1';
        CIN_s <= '0';
        wait for 10 ns;
        assert ( SUM_s = '0'  ) report "Failed Case 6 - SUM" severity error;
        assert ( COUT_s = '1' ) report "Failed Case 6 - COUT" severity error;
        wait for 40 ns;

        -- Case 7 : 1+1 with carry in of 1.
        A_s <= '1';
        B_s <= '1';
        CIN_s <= '1';
        wait for 10 ns;
        assert ( SUM_s = '1'  ) report "Failed Case 7 - SUM" severity error;
        assert ( COUT_s = '1' ) report "Failed Case 7 - COUT" severity error;
        wait for 40 ns;

    end process;
END TEST;

但是出现此错误:

错误(10533):add_test.vhd(65)处的VHDL Wait语句错误:Wait语句必须包含带UNTIL关键字的条件子句

1 回答

  • 1

    正如Brian所提到的,Altera Quartus是一个综合工具:它将您的VHDL(或Verilog)代码转换为"netlist",可以映射到实际门上(或者在FPGA的情况下查找表,但这是另一个故事) . 因此,Quartus就像是来自Xilinx的并发ISE . 还有其他合成器,例如Synopsys的Design Compiler等 . 通常,您可以在VHDL(或Verilog)中进行设计,以实现此目的:获得最终工作的硬件,实际门(FPGA或ASIC门) .

    但在此之前,您还需要检查此电路是否有可能真正发挥作用:为此您需要一个测试台 . 一般来说,这个测试平台是 not synthesizable :它只是一组进程:

    • 生成所有必需的时钟并重置

    • 用数据提供"design under test"(DUT)

    • 在完成自己的计算后回读数据

    构建测试平台本质上是一个软件学科 . 上述过程充当虚拟仪器,使您的DUT进入预期状态 .

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