你看，我已经完成了用modelim在vhdl上描述一个ALU，但是测试平台似乎没有更新解决方案，当我看到模拟电路32位响应总是说 "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" 我不知道我写错了什么testbench还有编译器关于电路响应的警告
**警告：（vsim-8683）未初始化的端口/ alu_tb / ALU_test / res（32 downto 0）没有驱动程序 . 该端口将为信号网络贡献 Value （UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU） .
这是测试平台代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU_tb is
end ALU_tb;
architecture bhv_ALU_tb of ALU_tb is
component ALU
port(
a, b: in std_logic_vector(31 downto 0);
c: in std_logic;
s: in std_logic_vector(3 downto 0);
res: out std_logic_vector(32 downto 0));
end component;
signal a, b: std_logic_vector(31 downto 0);
signal c: std_logic;
signal s: std_logic_vector(3 downto 0);
signal re: std_logic_vector(32 downto 0);
begin
ALU_test: ALU port map (a => a, b => b, c => c, s => s, res => re);
process begin
b <= "00000000000010100111010100011110";
a <= "00000000011010000100110011101110";
c <= '0';
s <= "1111";
wait for 2 ns;
b <= "00000000000010100111010100011110";
a <= "00000000011010000100110011101110";
c <= '0';
s <= "0100";
wait for 2 ns;
s <= "0000";
wait for 2 ns;
s <= "0001";
wait for 2 ns;
s <= "0010";
wait for 2 ns;
s <= "0011";
wait for 2 ns;
s <= "0100";
wait for 2 ns;
s <= "0101";
wait for 2 ns;
s <= "0110";
wait for 2 ns;
s <= "0111";
wait for 2 ns;
s <= "1000";
wait for 2 ns;
s <= "1001";
wait for 2 ns;
s <= "1010";
wait for 2 ns;
s <= "1011";
wait for 2 ns;
s <= "1100";
wait for 2 ns;
s <= "1101";
wait for 2 ns;
s <= "1110";
wait for 2 ns;
s <= "1111";
wait for 2 ns;
end process;
end bhv_ALU_tb;
我知道这个错误似乎是微不足道的“res没有被初始化”但是我已经远离了vhdl太长时间并且老实说不知道如何修复它，任何想法？
1 回答
首先
坏..不要't use. You don'甚至需要他们在这个文件中 . 如果您需要arithmentic，请使用
numeric_std.然后：错误在组件
ALU中，因为它应该'drive'res. 但既然你没有发布那个代码，我们就无法帮助你了 .附：目前，您不再需要在VHDL中定义组件 . 你可以写：