嘿伙计们我正在使用VHDL,我的问题陈述如下:
Write a VHDL code for XOR and XNOR functions, same as previous lab session, and define another input “x” in your code such that if input x=1 then F = X1 XOR X2, else F = X1 XNOR X2.
所以我开始编写这段代码:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY prework IS
PORT ( x1, x2, x : IN STD_LOGIC ;
f: OUT STD_LOGIC ) ;
END prework ;
ARCHITECTURE LogicFunction OF prework IS
PROCESS (x,x1,x2)
BEGIN
if x = '1' then
f <= (x1 AND NOT x2) OR (NOT x1 AND x2);
else
f <= NOT((x1 AND NOT x2) OR (NOT x1 AND x2));
end if;
end PROCESS;
END LogicFunction ;
但我不断收到这些错误:
错误(10500):prework.vhd(16)附近文本“PROCESS”的VHDL语法错误;期待“开始”或声明
错误(10500):prework.vhd(20)附近文本“ELSE”的VHDL语法错误;期望“结束”,或“(”或标识符(“else”是保留关键字)或并发语句
错误(10500):prework.vhd(22)的VHDL语法错误接近文本“if”;期待“;”或标识符(“if”是保留关键字)或“架构”
那么请你帮我解决一下这些错误,谢谢
1 回答
在
Architecture
语句之后,您还必须使用Begin
,就像Process
之后一样 . 错误很清楚 .