Vhdl在模拟中使用加法器减法器U向上计数器

我试图使用结构建模使用4位加法器减法器制作一个四位向上计数器问题是加法器减法器的输入（A）需要更新为等于总和，我试图在过程中创建信号解决这个问题，但它在模拟中给出了U我也不能设置为等于输出，但我不得不写出输出等于A

此外，警告信号s为0，我需要它改变0和1，因为它负责向上计数，但是当我尝试在测试台中为它设置值时它会给出错误

我无法弄明白，任何帮助都非常感谢

模拟错误：错误：Xst：528 - 信号单位中的多源>;此信号连接到多个驱动程序 . 错误：Xst：528 - 信号单位中的多源>;此信号连接到多个驱动程序 . 错误：Xst：528 - 信号单位中的多源>;此信号连接到多个驱动程序 . 错误：Xst：528 - 信号单位中的多源>;此信号连接到多个驱动器

模拟警告：从不使用输入 . 如果该端口属于顶级块或者属于子块并保留该子块的层次结构，则该端口将被保留并保持未连接状态 . 警告：Xst：653 - 使用信号但从未分配信号 . 此无源信号将自动连接到值0 .

This is the counter code 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity upDown is
    Port ( a: in STD_LOGIC_VECTOR(3 downto 0 );
             b : in STD_LOGIC_VECTOR(3 downto 0 );
            clk,reset,enable : in  STD_LOGIC  ;
           o : out STD_LOGIC_VECTOR(3 downto 0 )
            );
end upDown;

architecture Behavioral of upDown is

component addersub4bits is 
 Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
        y : out  STD_LOGIC_VECTOR (3 downto 0);
        s : in  STD_LOGIC  );
 end component ;

 signal s : STD_LOGIC ;
-- signal tmp2 : STD_LOGIC_VECTOR(3 downto 0) ;
signal outputsignal: STD_LOGIC_VECTOR(3 downto 0) ; --inside process

begin

ad : addersub4bits  port map( a,"0001" ,outputsignal ,s) ;

process (clk,reset,enable) 

begin

if(reset= '1' ) 
then outputsignal <= "0000"; 

elsif(clk' event and clk='1' ) then 
if(enable ='1' ) then 
outputsignal<=a ;

else

outputsignal<=outputsignal ;   --zay mahowa 
end if ;
end if ;
end process ;
--o <= tmp ;
o <=outputsignal ;

end Behavioral ;

加法器减法器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity addersub4bits is
Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
y : out  STD_LOGIC_VECTOR (3 downto 0);
s : in  STD_LOGIC);

end addersub4bits;

architecture dataflow of addersub4bits is


begin

 Process(a,b,s) 
 begin
if (s='1') then 

y<= (a + b) ;

else
y<=(a-b) ;

end if ; 

end process ;


end dataflow;

试验台

-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY uD_testbench IS
END uD_testbench;

ARCHITECTURE behavior OF uD_testbench IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT upDown
    PORT(
         a : IN  std_logic_vector(3 downto 0);
         b : IN  std_logic_vector(3 downto 0);
         clk : IN  std_logic;
         reset : IN  std_logic;
         enable : IN  std_logic;
         o : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal a : std_logic_vector(3 downto 0) := (others => '0');
   signal b : std_logic_vector(3 downto 0) := (others => '0');
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal enable : std_logic := '0';

    --Outputs
   signal o : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: upDown PORT MAP (
          a => a,
          b => b,
          clk => clk,
          reset => reset,
          enable => enable,
          o => o
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for 100 ns ;
        clk <= '1';
        wait for 100 ns ;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      reset <= '1' ;enable <= '0' ; wait for 150 ns ;
        reset <= '0'; wait for 300 ns ;

        --enable <= '0' ; wait for 200 ns ;
        enable <='1' ;wait ;
   end process;

END;