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将std_logic_vector与多个常量进行比较

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我有一个if子句，我希望将6位std_logic_vector与多个常量任意（即未运行的数字）6位值进行比较 . 我知道我可以用“|”在结构的情况下，但有没有办法在保持if语句的同时缩短以下内容？我不是100％肯定，但我认为设计的其余部分是使用VHDL93 .

if not (de_inst(31 downto 30) = FMT3 and (
  de_inst(24 downto 19) = LDSB or
  de_inst(24 downto 19) = LDSH or
  de_inst(24 downto 19) = LDUB or
  de_inst(24 downto 19) = LDUH or
  de_inst(24 downto 19) = LD or
  de_inst(24 downto 19) = LDD or
  de_inst(24 downto 19) = STB or
  de_inst(24 downto 19) = STH or
  de_inst(24 downto 19) = ST or
  de_inst(24 downto 19) = ISTD or
  de_inst(24 downto 19) = IAND or
  de_inst(24 downto 19) = ANDN or
  de_inst(24 downto 19) = IOR or
  de_inst(24 downto 19) = ORN or
  de_inst(24 downto 19) = IXOR or
  de_inst(24 downto 19) = IXNOR or
  de_inst(24 downto 19) = ISLL or
  de_inst(24 downto 19) = ISRL or
  de_inst(24 downto 19) = ISRA or
  de_inst(24 downto 19) = IADD or
  de_inst(24 downto 19) = ISUB or
  de_inst(24 downto 19) = UMUL or
  de_inst(24 downto 19) = SMUL or
  de_inst(24 downto 19) = UDIV or
  de_inst(24 downto 19) = SDIV )) then
vhdl

1 回答

  • 0

    VHDL允许您在更高级别编写它，在其中您对所有指令进行“设置”，然后检查信号是否具有这些指令之一的值，例如，沿着以下行：

    subtype inst_t is std_logic_vector(5 downto 0);
constant LDSB  : inst_t := "000000";  -- Just some value
...
type inst_array_t is array(natural range <>) of inst_t;
constant INST_SET : inst_array_t := (LDSB, ...);
...
function in_set(sig : inst_t; set : inst_array_t) return boolean is
  variable res_v : boolean;
begin
  res_v := FALSE;
  for idx in set'range loop
    res_v := res_v or (sig = set(idx));
  end loop;
  return res_v;
end function;
...
if not ((de_inst(31 downto 30) = FMT3) and 
        in_set(de_inst(24 downto 19), INST_SET)) then
  ...
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