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如何在VHDL中初始化std_logic_vector？

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我有一个std_logic_vector（4096 downto 0）信号，我想初始化它如下：

architecture Behavioral of test is

    type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
    signal ram : ram_type;
    ram(0) := "0010000000000100";   
    ram(1) := "0001000000000101";
    ram(2) := "0011000000000110";
    ram(3) := "0111000000000001";
    ram(4) := "0000000000001100";
    ram(5) := "0000000000000011";
    ram(6) := "0000000000000000";
    ram(4095 downto 7) := (others => (others => '0'));
    begin
   "some code"
end behavioral

由于某种原因，我需要用这些值初始化它（我不能将这些值赋值给它，它必须被初始化）是否有任何方法可以做到这一点？我尝试了上面的代码，它没有用

vhdl hdl xilinx-ise

1 回答

  • 4

    ram 可以初始化为：

    architecture Behavioral of test is
    type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
    signal ram : ram_type := (0 => "0010000000000100",
                              1 => "0001000000000101",
                              2 => "0011000000000110",
                              3 => "0111000000000001",
                              4 => "0000000000001100",
                              5 => "0000000000000011",
                              6 => "0000000000000000",
                              others => (others => '0'));
begin
  -- Concurrent code
end Behavioral;

    但是，您可能需要查看特定的FPGA和工具功能，以查看是否有一些特定方式应将初始化值提供给RAM，以便综合工具可以正确映射它 .

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