我正在尝试在Verilog中编写IEEE 754单精度浮点除法格式的代码,然后合成以便能够在ZedBoard上实现它下面的一个显示了IEEE 754除法的计算公式
X3= (X1/X2)
= ((-1)^S1 (M1 x 2E1)) / ((-1) S2 (M2 x 2E2))
= (-1)^S3 (M1/M2) 2 (E1-E2)
Here how to find M1/M2 in general? Is there any algorithm to calculate M1/M2 (in particular for single precision)?
Things I know currently:
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符号位可以通过对被除数和除数的符号位进行异或来完成
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指数可以计算为从除数的除数中减去除数的指数,然后加上偏差(在单精度的情况下为127)
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我知道's not about using some division algorithm to just send M1 and M2 as dividend and divisor (ie., it'不只是在M1和M2上应用整数除法
Things I wanted to know:
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找到M1 / M2的算法
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如何在Verilog中实现(以便可以合成)?