作为对Artix-7 FPGA上现有大型设计的改编的一部分，我实现了一个简单的计数机制，类似于“带有'常数'的Archticture”，因此在将来，我可以只改变常量的值而不是过分担心它的使用位置 .

然而，它导致了几次定时故障，我回到正常的方式来增加一个计数器，通过添加1来解决时序故障 . 以下是我尝试在Vivado 2016.4工具中合成的实体和2个体系结构 . 但是Vivado中的Project Summary选项卡显示除了使用IO之外没有任何资源 . 所以我的问题是，在VHDL中声明常量会导致比平常更多的硬件吗？两种实现有什么区别？

Entity

entity counter is
Port(
      i_clk : in std_logic;
      i_rst : in std_logic;
      o_cnt : out std_logic_vector(7 downto 0)
    );
end counter;

Architecture with 'constant'

architecture Behavioral of counter is
signal s_cnt : unsigned(7 downto 0) := (others => '0');
signal s_max : unsigned(7 downto 0) := (others => '1');

constant c_INCR : unsigned(3 downto 0) := x"1";
begin
process (i_clk) begin
    if rising_edge(i_clk) then
        if i_rst = '1' then
            s_cnt <= (others => '0');
        else
            o_cnt <= std_logic_vector(s_cnt);
            if s_cnt = s_max then
                s_cnt <= (others => '0');
            else
                s_cnt <= s_cnt + c_INCR;
            end if;
        end if;
    end if;
end process;

end Behavioral;

Architecture with '+1'

architecture Behavioral of counter is
signal s_cnt : unsigned(7 downto 0) := (others => '0');
signal s_max : unsigned(7 downto 0) := (others => '1');

begin
process (i_clk) begin
    if rising_edge(i_clk) then
        if i_rst = '1' then
            s_cnt <= (others => '0');
        else
            o_cnt <= std_logic_vector(s_cnt);
            if s_cnt = s_max then
                s_cnt <= (others => '0');
            else
                s_cnt <= s_cnt + 1;
            end if;
        end if;
    end if;
end process;

end Behavioral;
vhdl fpga synthesis vivado