library ieee;
use ieee.std_logic_1164.all;
entity basic_shift_register_with_multiple_taps is
generic
(
DATA_WIDTH : natural := 8
);
port
(
clk : in std_logic;
enable : in std_logic;
sr_one : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_two : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_out : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
);
end entity ;
architecture rtl of basic_shift_register_with_multiple_taps is
signal sig_out :std_logic_vector(2*(DATA_WIDTH-1) downto 0);
variable count : integer := 0;
variable count1 : integer := 0;
begin
process (clk,enable,sr_one,sr_two,sig_out)
begin
if(enable = '0' or count = 16) then
count := 0;
count1 := 0;
else if (clk'event and clk='1') then
sig_out(count) <= sr_one(count1);
count := count + 1;
else --if (clk'event and clk='0') then--
sig_out(count) <= sr_two(count1);
count := count + 1;
end if;
count1 := count1 + 1;
(54) end process;
sr_out <= sig_out;
(58) end rtl;
错误:
错误(10500):teste.vhd(54)附近文本“process”的VHDL语法错误;期待“if”错误(10500):teste.vhd(58)附近文本“rtl”的VHDL语法错误;期待“如果”
1 回答
你的问题是你的第二个if语句
没有
end if
与之关联 . 因此,当编译器到达第54行时,它会在end if
之前遇到end process
. 而不是这个做这个:
但是,如果您打算合成这个,那么您的语法错误是您最不担心的 . 见this answer .