我试图编写一个奇怪的VHDL，它接受4个值，并且根据一个输入的值将使用几种不同的方法创建两个平均值，并输出该特定方法的8个最高有效位 .
我正在使用Xilinx Vivado和XSim .
我在使用整数的早期，不太复杂的修订版中，我的代码运行正常 . 但是，由于项目的要求，我被告知必须使用std_logic_vectors作为输出 .
当我尝试在一次分配中进行多次添加时，我的问题出现了，我不确定这是不可能的，还是我只是错误地解决了这个问题 .
这是我的代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity binning_unit is
port(
A_DATA : in STD_LOGIC_VECTOR (12 downto 0); -- Imager a pixel data
B_DATA : in STD_LOGIC_VECTOR (12 downto 0); -- Imager b pixel data
C_DATA : in STD_LOGIC_VECTOR (12 downto 0); -- Imager c pixel data
D_DATA : in STD_LOGIC_VECTOR (12 downto 0); -- Imager d pixel data
MODE : in STD_LOGIC_VECTOR (1 downto 0); -- Binning unit mode
LVAL : in STD_LOGIC; -- Data available for read on ABCD ports
DATA_AC : out STD_LOGIC_VECTOR (7 downto 0) := x"00"; -- Binning unit AC output externalized
DATA_BD : out STD_LOGIC_VECTOR (7 downto 0) := x"00" -- Binning unit BD output externalized
);
end binning_unit;
architecture behavior of binning_unit is
signal DATA_AC_INT : unsigned (14 downto 0) := (others => '0');
signal DATA_BD_INT : unsigned (14 downto 0) := (others => '0');
begin
------------------------------------------------------------------------------------------------
-- Process Description: Creates various simplified outputs via the use of one of several
-- data binning techiniques. Values are only available when LVAL is
-- high.
--
-- Possible values for MODE:
-- "00" - 2x2 adding mode. Creates 1kx1 pixel output by adding all 4 values per sample
-- "01" - No adding AB pass-through mode. Simulates 2kx1 pixel output by ignoring CD pixel row
-- "10" - 1x2 adding mode. Creates 2kx1 pixel output by adding AC and BD values per sample
------------------------------------------------------------------------------------------------
process (A_DATA, B_DATA, C_DATA, D_DATA, MODE, LVAL)
begin
if LVAL = '1' then
case MODE is
when "00" =>
DATA_AC_INT <= (unsigned(A_DATA) + unsigned(B_DATA) + unsigned(C_DATA) + unsigned(D_DATA)); -- Add all four pixels
DATA_BD_INT <= (unsigned(A_DATA) + unsigned(B_DATA) + unsigned(C_DATA) + unsigned(D_DATA)); -- Add all four pixels
when "01" =>
DATA_AC_INT <= "00" & unsigned(A_DATA); -- Ignore CD line
DATA_BD_INT <= "00" & unsigned(B_DATA); -- Ignore CD line
when "10" =>
DATA_AC_INT <= '0' & (unsigned(A_DATA) + unsigned(C_DATA)); -- Add parallel pixels from both lines
DATA_BD_INT <= '0' & (unsigned(B_DATA) + unsigned(D_DATA)); -- Add parallel pixels from both lines
when others =>
DATA_AC_INT <= (others => '0');
DATA_BD_INT <= (others => '0');
end case;
else
DATA_AC_INT <= (others => '0');
DATA_BD_INT <= (others => '0');
end if;
end process;
DATA_AC <= STD_LOGIC_VECTOR("00" & DATA_AC_INT(14 downto 9)) when MODE = "00" else -- Use top 6 useful bits shifted right twice (Divide by 4)
STD_LOGIC_VECTOR(DATA_AC_INT(12 downto 5)) when MODE = "01" else -- Use top 8 useful bits
STD_LOGIC_VECTOR('0' & DATA_AC_INT(13 downto 7)) when MODE = "10"; -- Use top 7 useful bits shifted right once (Divide by 2)
DATA_BD <= STD_LOGIC_VECTOR("00" & DATA_BD_INT(14 downto 9)) when MODE = "00" else -- Use top 6 useful bits shifted right twice (Divide by 4)
STD_LOGIC_VECTOR(DATA_BD_INT(12 downto 5)) when MODE = "01" else -- Use top 8 useful bits
STD_LOGIC_VECTOR('0' & DATA_BD_INT(13 downto 7)) when MODE = "10"; -- Use top 7 useful bits shifted right once (Divide by 2)
end behavior;
我的测试台：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binning_unit_test is
begin
end binning_unit_test;
architecture Behavior of binning_unit_test is
component binning_unit is
port(
A_DATA : in STD_LOGIC_VECTOR (12 downto 0); -- Imager a pixel data
B_DATA : in STD_LOGIC_VECTOR (12 downto 0); -- Imager b pixel data
C_DATA : in STD_LOGIC_VECTOR (12 downto 0); -- Imager c pixel data
D_DATA : in STD_LOGIC_VECTOR (12 downto 0); -- Imager d pixel data
MODE : in STD_LOGIC_VECTOR (1 downto 0); -- Binning unit mode
LVAL : in STD_LOGIC; -- Data available for read ABCD ports
DATA_AC : out STD_LOGIC_VECTOR (7 downto 0); -- Binning unit AC output
DATA_BD : out STD_LOGIC_VECTOR (7 downto 0) -- Binning unit BD output
);
end component binning_unit;
signal A_DATA : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal B_DATA : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal C_DATA : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal D_DATA : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal MODE : STD_LOGIC_VECTOR (1 downto 0) := "01";
signal LVAL : STD_LOGIC := '0';
signal DATA_AC : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal DATA_BD : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin
binning_unit1: component binning_unit
port map(
A_DATA => A_DATA,
B_DATA => B_DATA,
C_DATA => C_DATA,
D_DATA => D_DATA,
MODE => MODE,
LVAL => LVAL,
DATA_AC => DATA_AC,
DATA_BD => DATA_BD
);
A_DATA <= "0000000000001";
B_DATA <= "0000000000001";
C_DATA <= "0000000001111";
D_DATA <= "0000000001111";
-- MODE <= "00", "01" after 20 NS, "10" after 40 NS,
-- "11" after 60 NS;
LVAL <= '1', '0' after 10 NS, '1' after 20 NS,
'0' after 30 NS, '1' after 40 NS,
'0' after 50 NS, '1' after 60 NS;
end architecture Behavior;
如果我使用MODE =“00”，它会尝试将所有4个加在一起，模拟将停止并且我得到的错误是
ERROR: Array sizes do not match, left array has 15 elements, right array has 13 elements.
添加4个13位数应该是15位，所以我不确定这里有什么问题 . 任何人都可以对此分享一些见解吗？是不是可以为unsigned多次添加？如果您需要更多信息，请与我们联系 .
谢谢