如何在Xilinx中定义时钟输入

2 回答

• 2

  看看这个例子 .

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;    -- for the unsigned type
  
  entity counter_example is
  generic ( WIDTH : integer := 32);
  port (
    CLK, RESET, LOAD : in std_logic;
    DATA : in  unsigned(WIDTH-1 downto 0);  
    Q    : out unsigned(WIDTH-1 downto 0));
  end entity counter_example;
  
  architecture counter_example_a of counter_example is
  signal cnt : unsigned(WIDTH-1 downto 0);
  begin
    process(RESET, CLK) is
    begin
      if RESET = '1' then
        cnt <= (others => '0');
      elsif rising_edge(CLK) then
        if LOAD = '1' then
          cnt <= DATA;
        else
          cnt <= cnt + 1;
        end if;
      end if;
    end process;
  
    Q <= cnt;
  
  end architecture counter_example_a;
  

  Source

  回复于 2024-05-06T06:44:09+08:00
• 2

  想象一下，您有一个样本设备如下：

  ENTITY SampleDevice IS 
      PORT 
      ( 
          CLK : IN std_logic
      );
  END SampleDevice;
  

  为了将CLK信号连接到FPGA中的实时时钟输入，您应将其设置为Top Module并创建带有条目的UCF文件：

  NET "CLK"  LOC = "P38";
  

  P38是Xilinx Spartan 3 XC3S200的时钟输入 .

  回复于 2024-05-06T06:44:09+08:00