我试图找出为什么这个测试台没有使用模拟时分配的触发器 .

这是我创建的D触发器：

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity dff_hw is
     port (clk : in std_logic;
             rst : in std_logic;
             d : in std_logic;
             q : out std_logic);
end dff_hw;
architecture Behavioral of dff_hw is
    begin
     dff_hw_proc : process (clk, rst)
         begin
         if (rst = '1') then
             q <= '0';
         elsif rising_edge(clk) then
                q <= d;
         end if;
     end process dff_hw_proc;
end architecture Behavioral;

这是我写的测试台：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity hw_dff_tb is
end hw_dff_tb;
architecture behavior of hw_dff_tb is
     -- Component Declaration for the Unit Under Test (UUT)
     component hw_dff
         port(
         clk : in std_logic;
         rst : in std_logic;
         d : in std_logic;
         q : out std_logic
         );
     end component;

 --Inputs
 signal hw_dff_tb_clk : std_logic := '0';
 signal hw_dff_tb_rst : std_logic := '0';
 signal hw_dff_tb_d : std_logic := '0';

 --Outputs
 signal hw_dff_tb_q : std_logic;

 -- Clock period definitions
 constant hw_dff_tb_clock_period : time := 10ns;

begin
     -- Instantiate the Unit Under Test (UUT)
     uut : hw_dff port map (
         clk => hw_dff_tb_clk,
         rst => hw_dff_tb_rst,
         d => hw_dff_tb_d,
         q => hw_dff_tb_q);
     -- Clock process definitions
     hw_dff_clock_process : process
     begin
         hw_dff_tb_clk <= '0';
         wait for hw_dff_tb_clock_period/2;
         hw_dff_tb_clk <= '1';
         wait for hw_dff_tb_clock_period/2;
 end process;
 -- Stimulus process
 stim_proc : process
 begin
         -- hold reset state for 100us.
         hw_dff_tb_rst <= '1';
         hw_dff_tb_d <= '0';
         wait for hw_dff_tb_clock_period*2;
         hw_dff_tb_rst <= '0';

         wait for hw_dff_tb_clock_period*1;
         hw_dff_tb_d <= '1';

         wait for hw_dff_tb_clock_period*1;
         hw_dff_tb_d <= '0';

          wait for hw_dff_tb_clock_period*1;
         hw_dff_tb_d <= '1';

         wait for hw_dff_tb_clock_period*1;
         hw_dff_tb_d <= '0';

         wait;
     end process;
end;

当我运行模拟时，q输出没有做任何事我甚至试图将它在触发器文件中设置为1并且在我运行该测试的整个时间它保持为0 . 我知道，因为它没有按照设计工作我做错了什么，但是对VHDL不熟悉我不知道我需要谷歌找出导致该部分没有“插入”测试台的原因 .

vhdl fpga