如何为VHDL仿真输入所需的输入（强制命令）

以下是使用D触发器的计数器的VHDL代码 . 这里我们假设触发器是正边沿触发的 .

在架构内部，我将Q（当前状态）和D声明为4位逻辑向量 .

我分配了所有输出（Z0到Z7）和D信号值，以分别匹配由计数器和触发器的最小输入公式确定的逻辑表达式 .

在代码结束时，调用一个进程来模拟clear（ClrN）和clock（CLK）的行为

My Question:

代码工作正常但我遇到了 Simulation of the test bench 的问题 .

在模拟中，我们需要显示以状态1000开始的电路，然后以正确的顺序通过每个状态 .

In Short: How do i show the signals Q and D in the simulation. This is the part i am not sure on how to do.

有人告诉我使用force命令设置所需的输入 .

例如：

force ClrN 0 0, 1 20  
force CLK 1000 0  
force CLK 0 0, 1 40 -repeat 80

但我不知道在哪里以及如何使用它 .

Below is the VHDL Code:

library IEEE;  
use IEEE.STD_LOGIC_1164.ALL;

entity counter is
port (CLK, ClrN : in std_logic;  
        Z0 : out std_logic;  
        Z1 : out std_logic;  
        Z2 : out std_logic;  
        Z3 : out std_logic;  
        Z4 : out std_logic;  
        Z5 : out std_logic;  
        Z6 : out std_logic;  
        Z7 : out std_logic);  
end counter;

architecture Behavioral of counter is

signal Q: std_logic_vector(0 to 3);
signal D: std_logic_vector(0 to 3);

begin

u1: process(Q)

begin

Z0 <= Q(0) and not Q(1) and not Q(3);
Z1 <= Q(0) and Q(1);
Z2 <= not Q(0) and Q(1) and not Q(2);
Z3 <= Q(1) and Q(2);
Z4 <= not Q(1) and Q(2) and not Q(3);
Z5 <= Q(2) and Q(3);
Z6 <= not Q(0) and not Q(2) and Q(3);
Z7 <= Q(0) and Q(3);

D(0) <= not Q(1) and not Q(2);
D(1) <= not Q(2) and not Q(3);
D(2) <= not Q(0) and not Q(3);
D(3) <= not Q(0) and not Q(1);
end process u1;


u2: process(CLK,ClrN)  
begin  
if ClrN = '0' then  
Q <= "1000";  
elsif Rising_Edge (CLK) then  
Q <= D;  
end if;  
end process u2;  

end Behavioral;

The following is my VHDL test bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS 

    COMPONENT counter
    PORT(
         CLK : IN  std_logic;
         ClrN : IN  std_logic;
         Z0 : OUT  std_logic;
         Z1 : OUT  std_logic;
         Z2 : OUT  std_logic;
         Z3 : OUT  std_logic;
         Z4 : OUT  std_logic;
         Z5 : OUT  std_logic;
         Z6 : OUT  std_logic;
         Z7 : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal CLK : std_logic := '0';
   signal ClrN : std_logic := '0';

    --Outputs
   signal Z0 : std_logic;
   signal Z1 : std_logic;
   signal Z2 : std_logic;
   signal Z3 : std_logic;
   signal Z4 : std_logic;
   signal Z5 : std_logic;
   signal Z6 : std_logic;
   signal Z7 : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: counter PORT MAP (
          CLK => CLK,
          ClrN => ClrN,
          Z0 => Z0,
          Z1 => Z1,
          Z2 => Z2,
          Z3 => Z3,
          Z4 => Z4,
          Z5 => Z5,
          Z6 => Z6,
          Z7 => Z7
        );

   -- Clock process definitions
   CLK_process :process
   begin
        CLK <= '0';
        wait for CLK_period/2;
        CLK <= '1';
        wait for CLK_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin        
--      -- hold reset state for 10 ns.

      wait for 10 ns;   

        ClrN <= '1'; 

     wait;
   end process;

END;

在何处以及如何将Q和D信号添加到我的测试平台以获得模拟，该模拟显示电路从状态1000开始，然后以正确的顺序通过每个状态 . 我甚至使用force命令？