FIFO错误：找不到控制信号 - VHDL

我找到了一个VHDL FIFO代码并尝试修改它以使用两个不同的时钟，一个用于写入，一个用于读取 . 我已经尝试了代码并且似乎在模拟中工作，但是当我尝试合成它时，我得到了这个错误：

“找不到Full的控制信号”

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity FIFO is
    Generic (
        constant DATA_WIDTH  : positive := 8;
        constant FIFO_DEPTH : positive := 100
    );
    Port ( 
        WCLOCK      : in  STD_LOGIC;
        RCLOCK      : in  STD_LOGIC;
        WriteEn : in  STD_LOGIC;
        DataIn  : in  STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
        ReadEn  : in  STD_LOGIC;
        DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
        Empty   : out STD_LOGIC;
        Full    : out STD_LOGIC;
        ModuleRESET : in STD_LOGIC
    );
end FIFO;

architecture FIFO_archi of FIFO is
    type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
    signal Memory : FIFO_Memory;
    signal Head : natural range 0 to FIFO_DEPTH - 1;
    signal Tail : natural range 0 to FIFO_DEPTH - 1;


    begin
         -- Memory Pointer Process
        process (WCLOCK, RCLOCK, ModuleRESET)
            variable Looped : boolean;
        begin
            if ModuleRESET = '0' then
                Head <= 0;
                Tail <= 0;
                Looped := false;
                Full  <= '0';
                Empty <= '1';
                DataOut <= (others => '0');
            elsif ReadEn = '1' then
                if rising_edge(RCLOCK) then                    
                    if ((Looped = true) or (Head /= Tail)) then
                        -- Update data output
                        DataOut <= Memory(Tail);

                        -- Update Tail pointer as needed
                        if (Tail = FIFO_DEPTH - 1) then
                            Tail <= 0;
                            Looped := false;
                            else
                                Tail <= Tail + 1;
                            end if;
                        end if;
                    end if;
                -- Update Empty and Full flags
                if (Head = Tail) then
                    if Looped then
                        Full <= '1';
                        else
                            Empty <= '1';
                        end if;
                    else
                        Empty   <= '0';
                        Full    <= '0';
                end if;
            elsif WriteEn = '1' then
                if rising_edge(WCLOCK) then   
                        if ((Looped = false) or (Head /= Tail)) then
                            -- Write Data to Memory
                            Memory(Head) <= DataIn;

                            -- Increment Head pointer as needed
                            if (Head = FIFO_DEPTH - 1) then
                                Head <= 0;
                                Looped := true;
                            else
                                Head <= Head + 1;
                            end if;
                        end if;
                -- Update Empty and Full flags
                if (Head = Tail) then
                    if Looped then
                        Full <= '1';
                        else
                            Empty <= '1';
                        end if;
                    else
                        Empty   <= '0';
                        Full    <= '0';
                end if;
                end if;
            end if;
        end process;

end FIFO_archi;

我怎么能解决这个错误？