我正在研究一个项目(VHDL) . 我已经生成了顶级模块的测试平台,其中包含 clk
和 reset
信号 . 当我没有't use reset in the process in the test bench my simulator shows the clock signals all the way up to 1000 ns (desired here) but as soon as I introduce reset, it'的长度减少到160 ns . 我无法理解这种行为 . 这是第一个测试台:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY toplevel_tb1 IS
END toplevel_tb1;
ARCHITECTURE behavior OF toplevel_tb1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pc_ins_cu_top
PORT(
clk : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '1';
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pc_ins_cu_top PORT MAP (
clk => clk,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
--reset <= '0';
wait for clk_period*100;
-- insert stimulus here
wait;
end process;
END;
在我的第二个测试平台中,我只是在 stim_proc : process
中取消注释 reset <= '0'
的行
这是图像: