我有一个文本文件，表示来自电路的整数格式的adc值，看起来像，

0000
0001
0005
3864
2290
1234
.
.
.
0002
0004
0006
4532
3457
.
.
.

前3个整数总是表示 Headers ，随后的256个整数值包含一个块 . 我编写了一个VHDL代码（算法）来分析这个文件，它存储了这个文件的几个特征 . 我还编写了一个测试平台，它读取文件并将一行中的每个值发送到分析器代码 . 这些值当前逐个发送到分析器组件，如我的测试平台代码中所述 .

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;



entity HFA_tb is
end HFA_tb;

architecture behave of HFA_tb is

--clock 100 MHz change to any value suitable
constant c_CLOCK_PERIOD : time:= 100 ns;
signal r_CLOCK      : std_logic  := '0';
--**signal r_ENABLE     : std_logic  := '0';
signal r_adcpulse   : integer; 
signal r_hitstart   : integer;   ---output of single threshold
signal r_hitend     : integer;
signal r_hitpeak    : integer;
signal r_peaktime   : integer;
signal r_hitsum     : integer;
signal r_opready    : std_logic := '0';





--more signal

--describe HFA component here (Unit Under Test)

component HFA is
 port (
   adcpulse_i     : in integer;
   clk          : in std_logic;
   hitstart_o   : out integer;   ---output of single threshold
   hitend_o     : out integer;
   hitpeak_o    : out integer;
   peaktime_o   : out integer;
   hitsum_o     : out integer;
   opready_o    : out std_logic

   );
 end component HFA;

begin

  --Instatiate the unit under test
  UUT : HFA
  port map (
    clk         => r_CLOCK,
    adcpulse_i    => r_adcpulse,
    hitstart_o  => r_hitstart,
    hitend_o    => r_hitend,
    hitpeak_o   => r_hitpeak,
    peaktime_o  => r_peaktime,
    hitsum_o    => r_hitsum,
    opready_o   => r_opready
  );

 p_CLK_GEN : process is
  begin
   wait for c_CLOCK_PERIOD/2;
   r_CLOCK <= not r_CLOCK;
 end process p_CLK_GEN;


  --main testing logic for reading from text file; feed in the loop and     check output

  process
   file in_buffer       :   text;
   file out_buffer      :   text;
   variable v_ILINE     :   line;
   variable v_OLINE     :   line;
   variable v_adcValue  :   integer;

  begin

    file_open(in_buffer,"test.txt",read_mode);

    file_open(out_buffer,"results.txt",write_mode);


    while not endfile(in_buffer) loop
      readline(in_buffer, v_ILINE);
      read(v_ILINE, v_adcValue);

      r_adcpulse <= v_adcValue;

      wait for c_CLOCK_PERIOD;

  end loop;

   if endfile(in_buffer) then

     write(v_OLINE, string'("hit_start_time"));
     writeline(out_buffer, v_OLINE);

     write(v_OLINE, r_hitstart);
     writeline(out_buffer, v_OLINE);

   end if;

  wait for c_CLOCK_PERIOD;

    file_close(in_buffer);

    file_close(out_buffer);

   wait;

  end process;  


 end behave;

从我的示例中可以看出，当前的测试平台只能一次读取一行并将其发送到分析器 . 我想要它做的是剥离 Headers （前3个整数）存储它，并在完成处理256个整数的一个块时再次将它连接到文本文件？任何提示都会在这方面有用 . 我的方法基于数据字比较器，data word description

vhdl fpga modelsim test-bench questasim